1. Field of the Invention
The present invention relates generally to an electrically erasable and programmable read only memory (hereinafter referred to as an EEPROM) and, more specifically, to an EEPROM of a NAND type and an operating method therefor.
2. Description of the Related Art
An EEPROM is usually used as a memory unit for a microcomputer.
FIG. 13 is a block diagram showing a known conventional EEPROM capable of writing/erasing electric information therein.
Referring to FIG. 13, the EEPROM comprises a memory array 50 including EEPROM cells; a row address buffer 51 receiving external row address signals; a column address buffer 52 receiving column address signals; a row decoder 53 and a column decoder 54 for decoding these address signals to provide a voltage to a word line and a bit line connected to a specified memory cell; a sense amplifier 56 for reading a signal stored in the memory cell designated by the two decoders through a column select gate 55; an output buffer 57 for outputting the read signal; and a control signal input buffer 58 receiving an external control signal to apply the same to each of the above mentioned portions.
In operation, the sense amplifier 56 amplifies a signal stored in a memory cell and applies the same to the output buffer 57. FIG. 14 is a schematic diagram showing examples of the memory array 50 and the column select gate 55 shown in FIG. 13.
Referring to FIG. 14, the column select gate 55 comprises a transistor 60 connected between an I/O line 59 and a bit line 31, and a transistor 63 connected between a CG line 61 and a control gate line 62. A column select gate signal Y2 is applied to the gates of the transistors 60 and 63. Transistors to which a column select gate signal Y1 is applied are connected in the similar manner.
4 bit memory cells are shown in the memory array 50. One memory cell comprises a memory transistor 6 having a floating gate and a selecting transistor 3 having its gate connected to a word line 32 for applying a signal stored in the memory transistor 6 to the bit line 31. Another selecting transistor 3a has its gate connected to the word line 32 and it is connected to apply a signal on the control gate line 62 to the gate of the memory transistor 6.
In operation, the memory transistor 6 stores a binary signal dependent on whether or not electrons are stored in the floating gate thereof. When electrons are stored, threshold voltage of the memory transistor 6 becomes high. Consequently, in the reading operation, the memory transistor 6 turns off. When electrons are not stored, the threshold voltage of the memory transistor 6 becomes negative. Consequently, the memory transistor 6 turns on in the reading operation.
A reading voltage from the sense amplifier is applied to the bit line 31 through the transistor 60 and it is further applied to the memory transistor 6 through the selecting transistor 3. Consequently, whether a current flows or not through the memory transistor 6 can be detected in the sense amplifier, whereby a signal stored in the memory transistor 6 can be read.
FIG. 15A is a plan view of a conventional EEPROM having a floating gate. FIG. 15B shows a cross sectional structure taken along the line XVB--XVB of FIG. 15A. The structure of the EEPROM will be described with reference to FIGS. 15A and 15B.
The EEPROM comprises a memory transistor 6 formed on a main surface of a P type silicon semiconductor substrate 20, and a selecting transistor 3. The memory transistor 6 comprises a tunnel impurity diffused region 9 formed on the main surface of the semiconductor substrate 20 which will be the drain region, a source region 2, a thin tunnel insulating film 16 formed on a prescribed region of the tunnel impurity diffused layer 9, a floating gate 14 formed of polysilicon on a region of the semiconductor substrate 20 including at least the tunnel insulating film 16 with an insulating film disposed therebetween, and a control gate 7 formed on the floating gate 14 with an interlayer silicon oxide film 15 disposed therebetween. The control gate 7, the floating gate 14 and the interlayer silicon oxide film 15 therebetween constitute a capacitor at a region in which they overlap with each other. The floating gate 14, the tunnel impurity diffused layer 9 connected to an impurity diffused layer 5 for connection and the tunnel insulating film 16 form a capacitor. In addition, the floating gate 14, the semiconductor substrate 20 and the insulating film near the tunnel insulating film 16 form a capacitor, except in the region of the tunnel insulating film 16. The floating gate 14 stores charges. Charging/discharging of the electric charges is carried out between the floating gate 14 and the tunnel impurity diffused layer 9 through the tunnel insulating film 16 in accordance with a voltage applied between the control gate 7 and the impurity diffused layer 5 for connection. The selecting transistor 3 comprises the impurity diffused layer 5 for connection and the drain region 1 formed spaced apart from each other on the main surface of the semiconductor substrate 20, and a selecting gate electrode 4 formed therebetween, which will be the word line. A selecting gate silicon oxide film 13 is formed between the selecting gate electrode 4 and the main surface of the semiconductor substrate 20. The drain region 1 is connected to the bit line 31 through a contact hole.
The selecting transistor 3 turns on/off in response to a signal applied through the selecting gate electrode 4. Consequently, the information stored in the memory transistor 6 connected to the selecting transistor 3 is read to the bit line 31.
The operation of the EEPROM will be described in the following. The EEPROM has three basic operation modes of reading, erasing and writing.
The table below shows voltages applied to respective elements in writing, erasing and reading charges representing information of the floating gate 14.
______________________________________ ELEMENTS READ ERASE WRITE ______________________________________ SELECTING GATE 5V V.sub.PP V.sub.PP ELECTRODE 4 CONTROL GATE 7 0V V.sub.PP OV BIT LINE 31 2V 0V V.sub.PP SOURCE LINE 12 0V 0V FLOATING FLOATING GATE 14 V.sub.F V.sub.E V.sub.W ______________________________________
In the table, V.sub.PP represents a programming voltage, V.sub.F represents a potential in a floating state, and V.sub.W and V.sub.E represent potentials of the floating gate 14 in respective operations.
As shown in the table, 5V is applied to the selecting gate electrode 4 in reading, 2V is applied to the bit line 31, and the control gate 7 and the source line 12 are grounded. In this condition, if the memory transistor 6 turns on or not is dependent on the potential of the floating gate 14. Therefore the condition of the floating gate 14 is decided by detecting the current flow of the source line 12. In erasing the memory cell, V.sub.PP is applied to the selecting gate electrode 4, while the bit line 31 and the source line 12 are grounded. In the erasing cycle, negative charges are applied to the floating gate 14. In writing, V.sub.PP is applied to the selecting gate electrode 4 and to the bit line 31, the control gate 7 is grounded and the source line 12 is kept at a floating state. Consequently, positive charges are introduced to the floating gate 14 to change the threshold voltage of the memory transistor 6.
FIGS. 16A and 16B are equivalent circuit diagrams of the EEPROM shown in FIGS. 15A and 15B. The reference character C.sub.1 represents a tunnel capacitance formed in the tunnel region. C.sub.2 represents a capacitor formed by the floating gate 14, the control gate 7 and the interlayer silicon oxide film 15 disposed therebetween. C.sub.3 represents a parasitic capacitance formed by the floating gate 14 out of the tunnel region, the tunnel impurity diffused layer 9 formed therebelow and the tunnel insulating film 16 formed therebetween. An equivalent circuit in the erasing mode is shown in FIG. 16B. In this case, the potential V.sub.F at the point F will be represented by the following equation, ##EQU1## is capacitive coupling ratio which is normally about 0.7. The electric field of the tunnel insulating film and the current flowing through the tunnel insulating film will be represented by the following equations. ##EQU2## EQU J=AE.sub.OX 2 exp (B/EOX) (3)
where
E.sub.OX represents thickness of the tunnel insulating film, PA1 J represents a current density value, and PA1 A and B represent constants.
By substituting the equation (2) by (1) with the capacitive coupling ratio 0.7 and T.sub.OX being 10 nm,
E.sub.OX =14MV/cm. By substituting the equation (3) with this value, a considerably large value of J is provided. Electrons are discharged/charged between the floating gate and the impurity region on the substrate by using the value of the electric field.
An overview of the conventional EEPROM has been described in the foregoing.
The conventional EEPROM was structured as described above. One memory cell must have one memory transistor, one transfer transistor and a set of source and drain electrodes, so that it is difficult to minimize the size of the cell.
One example of an EEPROM in which such drawbacks of the conventional EEPROM are eliminated is disclosed in "A New NAND Cell for Ultra High Density 5V-Only EEPROMs" R. Shirota et. al. Digest of Technical Papers for Symposium on VLSI Technology.
FIG. 17 is a plan view showing 1 byte of memory cells of the prior NAND type EEPROM disclosed therein. FIG. 18 is a cross sectional view of a portion taken along the line XIIX--XIIX of FIG. 17. Referring to FIGS. 17 and 18, the conventional NAND type EEPROM comprises a P type semiconductor substrate 20, a plurality of 1 byte of memory transistors 6 formed connected in series on the main surface of the substrate, a selecting transistor 3 for selecting the plurality of 1 bit of memory transistors as a whole formed on one end of the memory transistors 6 and a second selecting transistor 33 for applying a constant potential to the 1 byte of memory transistors. The memory transistor 6 comprises n.sup.+ impurity regions 34 which will be the source and the drain formed spaced apart from each other on the main surface of the semiconductor substrate 20, a floating gate 14 formed on a channel region sandwiched by the source and drain regions with a gate insulating film 35 disposed therebetween, and a control gate 7 formed on the floating gate 14 with an interlayer silicon oxide film 15 disposed therebetween. The gate insulating film 35 comprises a tunnel region 8 to cause Fowler-Nordheim tunnelling phenomenon (hereinafter simply referred to as F-N tunnelling phenomenon) between a tunnel impurity diffused layer 9 and the floating gate 14. The second selecting transistor 33 connects the 1 byte of memory cells to the ground through a source line 12.
FIG. 19 is an equivalent circuit diagram of the prior NAND type EEPROM shown in FIG. 17. 8 single bit memory transistors 6 constituting 1 byte are selected by one selecting transistor 3. The drain of the selecting transistor 3 is connected to the bit line 31. The control gates 7 of the memory transistors 6 are independent from each other and various voltages are applied thereto corresponding to the writing/reading of data. Each bit corresponds to the plan view of FIG. 17, and one example of such correspondence is represented by arrows in the figure.
FIG. 20 shows voltages applied to the control gate 7 of each memory transistor 6, the bit line 31 connected to the memory of 1 byte, the selecting transistor 3 and to the second selecting transistor 33 in writing data, erasing data and reading data to and from each of the memory transistors in the equivalent circuit shown in FIG. 19. Referring to FIG. 20, the operation of the prior art NAND type EEPROM will be described. It is assumed that the memory transistor represented by the arrow A is selected. In order to erase signals of all the bits of 1 byte, 13V is applied to all control gates 7 and 0V is applied to the bit line 31. Memory cells constituting a NAND column are erased in the order of the series connection of 1 byte. In depletion writing (usually called as "write" mode), 20V is applied to the control gates 7 between the selected bit line and the non selected memory transistor. 0V is applied to the control gate of the selected memory transistor and to the control gates of the non selected memory transistors which are between the selected memory transistor and the source region. Consequently, depletion writing is carried only on the selected bits. In a reading, 5V is applied to all non selected control gates. When the selected bit has been depleted, that portion becomes conductive. Consequently, presence/absence of a signal can be determined.
FIG. 21 shows changes of the threshold values of the memory transistors 6 when writing is carried out sequentially from the Bit 8 to the Bit 1 shown in FIG. 19. Since the writing is carried out sequentially, the absolute value of the threshold value increases as the writing proceeds from the Bit 8 to the Bit 1. Threshold value changes as a result of the change of the bulk resistance in the channel region.
Data reading operation of a conventional NAND type EEPROM having a serial byte structure (an EEPROM in which 1 byte comprises serially connected 8 memory cells) will be described in the following with reference to FIGS. 22 and 23. A plurality of strings ST are arranged in a matrix. The sense amplifier is provided for every line of strings arranged in the vertical direction. Each string ST stores 1 byte data. For example, the string ST.sub.11 surrounded by double solid lines store 8 bit data of D.sub.0 to D.sub.7. In the conventional NAND type EEPROM having the serial byte structure, writing/erasing is carried out sequentially in 8 cells connected in series in the direction of the bit line, as described above. Therefore, 1 byte must be arranged in series in one string.
The prior NAND type EEPROM structured as described above exhibits the following drawbacks.
First, it is presumed that the prior NAND type EEPROM has its tunnel region formed on the channel region, as shown in FIGS. 17 and 18. Therefore, the programming voltage applied to the memory transistor near the source is lowered by the channel resistance and the threshold value of other memory transistors. Consequently, writing cannot be fully carried out, and the threshold values of the memory transistors in one NAND type memory cell differ from each other. This is apparent from FIG. 21. For example, the threshold value of Bit 8 is -2V while the threshold value of Bit 1 is -6V. The difference of about 4V is generated in 1 byte. This means that the threshold values of all the memory cells in 1 byte are influenced by the threshold value of Bit 8 in manufacturing the memory cell, and therefore the reliability of the manufactured memory cells may be lowered. If the absolute value of the threshold becomes much larger than desired, the tunnel oxide film is degraded rapidly, shortening the life of the EEPROM because high voltage (such as 20V) has to be applied to the drain region adjacent to the memory transistor 6 to be written as shown in FIG. 20.
As shown in FIG. 20, 2 0V is applied to the control gates, that is, the word lines of the non-selected transistors from the drain to the selected memory transistor in writing. On this occasion, memory cells adjacent to the memory transistors to which 2 0V is applied are influenced. More specifically, the programming voltage V.sub.OPP =20V is applied not only to the non-selected word lines of the memory cells constituting a selected column but also to the gates of the transistor of the memory cells constituting a column not selected, corresponding one directly adjacent to the one with non-selected word line. There is a possibility of erroneous writing in a memory transistor intersecting the non-selected selected bit line which is at a different low level. In order to prevent the above mentioned erroneous writing when a high voltage is applied to a non-selected word line, an intermediate potential must be applied to all the non-selected bit lines. The 1 byte data arranged in series can only be read sequentially, as shown in FIG. 23. Therefore, the time required for reading is 8 times or more than that of reading 1 bit data. Namely, the reading of data requires much time.
In addition, since the tunnel region is formed on the channel, it becomes difficult to form diffused layers on both sides of the channel. Namely, the channel length cannot be determined in a self-alignment manner. Therefore, complicated processes such as overlapping of masking and so on are needed to form the tunnel region such as described above.